1. Field
Example embodiments relate to a semiconductor memory device, and more particularly, to a semiconductor memory device capable of increasing a self-refresh period during a self-refresh operation so as to reduce power consumption.
2. Description of the Related Art
In general, a memory cell of a semiconductor memory device may include, e.g., a NMOS transistor. Since the NMOS transistor may include a leakage current component, the semiconductor memory device may need to periodically restore data stored in the memory cell before the data is erased due to the leakage current.
The operation of periodically restoring data in the memory cell may be typically called a refresh operation. Especially, in a self-refresh operation, addresses for memory cells may be sequentially generated in a semiconductor memory device without using externally generated addresses used to address memory cells during a normal operation.